1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device and particularly, a NAND type flash memory.
2. Description of the Related Art
In recent years, in order to reduce the unit cost per one bit of data and increase storage capacity in a nonvolatile semiconductor memory device such as a NAND type flash memory, a flash memory which stores multi-bit data, that is, a volume of information of more than two levels of data, in one memory cell has been developed. In the case of storing four-levels (2 bits) of data in one memory cell, four threshold distributions of a memory cell exist corresponding to four-levels of data.
It is generally preferred that the form of the threshold distribution of a memory cell of this NAND type flash memory is sharp and narrow in width while considering drops in power supply voltage or a variations in manufacture. Consequently, because a memory cell has capacitive coupling with an adjacent memory cell, what is called interference of an adjacent memory cell occurs caused by programming of an adjacent memory cell and the width of a threshold distribution becomes wide. This influence is particularly prominent with miniaturization and becomes an obstacle to forming a more sharp and narrow threshold distribution when attempting to store multi-levels data.
Consequently, by narrowing the step-up width of a programming voltage Vpgm and programming, it is possible to reduce the widening of a threshold distribution. However, when narrowing the step-up width of a programming voltage Vpgm, the number of times the programming voltage Vpgm is applied increases, programming time becomes longer, programming speed is reduced. Therefore, guarantees of high speed programming while attempting to increase capacity by storing multi-levels data are being demanded. Japanese Laid Open Patent 2005-267687, Japanese Laid Open Patent 2005-267821, Japanese Laid Open Patent 2004-152405, Japanese Laid Open Patent 2004-327865 are used as reference.